1. Technical Field of the Invention
The present invention relates to a semiconductor integrated circuit with non-connection pins which are defined neither as an input/output nor as a voltage source.
2. Description of the Prior Art
Generally, the lead on chip (LOC) semiconductor device or chip on lead (COL) semiconductor device is supplied with the defined connection pins connected with input circuit, output circuit, and voltage source circuit, as well as the above-mentioned non-connection pins. Such non-connection pins are inevitably provided particularly in case of gate arrays to choose connections freely.
Further, LOC or COL semiconductor devices are supported on the lead frame which comprises connection pins and non-connection pins for wire bonding. Accordingly, the connection pins and the non-connection pins are extended to the positions for supporting the semiconductor chip.
Therefore, the non-connection pins are adjacent to the connection pins in the semiconductor device packaged by using the above-mentioned lead frame, wherein the non-connection pins are connected with the leads, extending on or under the semiconductor chip through an insulating film, which are not connected electrically with the internal circuit, while the connection pins are connected with the internal circuit electrically by the metal wires bonded with the lead.
If an abnormally high voltage is applied to the non-connection pins by static electricity, the insulating film in the semiconductor chip may suffer electrostatic breakdown by the discharge through the lead.
A semiconductor integrated circuit for preventing the electrostatic breakdown in the non-connection pins is disclosed in the Japanese Patent 61-180470(A) (1986)(Reference 1), wherein a surge voltage discharge circuit is connected to the lead which is connected to the non-connection pins.
There is also disclosed in the Japanese Patent 2-119171(A)(1990)(Reference 2) a semiconductor integrated circuit for preventing the electrostatic breakdown in the non-connection pins, wherein a protection means including a diode is connected with the connection line pattern.
Further, there is disclosed in the Japanese Patent 6-120426(A)(1994)(Reference 3) a master slice semiconductor integrated circuit with a protection diode circuit for preventing the electrostatic breakdown in the non-connection pins caused by the high voltage induced by a mutual inductance of the lead frame and the bonding wires, when a high voltage is applied to the connection pins which are adjacent to the non-connection pins.
On the contrary, a lead frame which can not support a semiconductor chip during the wire bonding is disclosed in the Japanese Patent 63-3463 (B2)(1988)(Reference 4), wherein the edges of the non-connection leads are more distant from the chip than the connection leads. Such a lead frame can afford some margin in positioning the lead frame and the semiconductor chip, because the spaces between the edge portions are wide.
As mentioned above, the non-connection pins are connected electrically with protection means to prevent the electrostatic breakdown of the non-connection pins by the electrostatic discharge, as disclosed in the References 1, 2 and 3. However, no consideration is taken with respect to the effect on the connection pins adjacent to the non-connection pins, although the breakdown of the non-connection pins is prevented.
Further, the Reference 4 does not point out any problem which arises in case of LOC or COL semiconductor devices wherein lead edges are connected on a chip, although it discloses a lead frame wherein the leads does not support a chip during wire bonding and the lead edges are not connected with the chip.
According to an experiment by the inventors of the present invention, it was confirmed that some voltages are induced in the connection pins adjacent to the non-connection pins which are supplied with high electrostatic voltages, probably because of the mutual inductance due to the inductances of the leads of the non-connection pins and the leads of the connection pins in the LOC or COL semiconductor devices. The inductance by the non-connection pins is not negligible any more, because the non-connection pins are long.
Further, it was found that the voltage induced on the connection pin is very high at the rise-up of the electrostatic voltage applied to the non-connection pin and then, decays rapidly and that this phenomenon results in the breakdown not only in the non-connection pins, but also in the internal circuit connected with the connection pins, for example, the insulating film of the gate of a MOSFET.
The electromotive force induced in the connection pin behaves differently from the electrostatic voltage applied to the non-connection pin. Therefore, different protection circuits are required for the non-connection pin and for the connection pin. Further, the electrostatic voltage applied to the non-connection pin was found to affect not only the adjacent connection pins, but also the other pins positioned at the opposite side of the connection pins.